module div1(clock,rst,clk_out1);
input clock,rst;
output clk_out1;
reg [25:0] m;
reg clk_out1;
always @(posedge clock)
begin
	if(!rst)
	begin clk_out1<=0; m<=0; end
	else
	begin
		m<=m+1;
		if(m==24999999) clk_out1<=~clk_out1;
		if(m==49999999) begin clk_out1<=~clk_out1; m<=0; end
	end
end
endmodule